1. Field of the Invention
The present invention relates to a liquid crystal display device and a pixel inspection method therefor, and more particularly to a liquid crystal display device and a pixel inspection method therefor that perform gray scale display using the combination of a plurality of subframes according to gray scale levels expressed by a plurality of bits.
2. Description of the Related Art
Heretofore, a subframe driving method is known as one of halftone display methods in liquid crystal display devices. In a subframe driving method which is one type of time base modulation methods, a predetermined period (one frame that is a unit for display of one image in the case of moving pictures, for example) is split into a plurality of subframes, and pixels are driven in a combination of subframes according to a gray scale to be displayed. The gray scale to be displayed is determined according to the ratio of a pixel drive period occupied in a predetermined period, and this ratio is specified by the combination of subframes.
In liquid crystal display devices according to this subframe driving method, one is known in which pixels are individually configured of a master latch, a slave latch, a liquid crystal display element, and first to third switching transistors, three transistors in total (see Japanese Patent Application National Publication (Laid-Open) No. 2001-523847, for example). In this pixel, one bit of a first data is applied to one input terminal of two input terminals of the master latch through the first switching transistor, a second data in the complementary relation with the first data is applied to the other input terminal through the second switching transistor, and when the pixel is selected by a row select signal applied through a row scanning line, the first data is written as the first and second switching transistors are turned to the ON-state. For example, when the first data has the logical value “1” and the second data has the logical value “0”, the pixel performs display.
After the data is written to all the pixels through the similar operations described above, the data written to the master latch are simultaneously read to the slave latch as the third switching transistors of all the pixels are turned to the ON-state in the subframe period, and the data latched to the slave latch are applied from the slave latch to the pixel electrode of the liquid crystal display element. The operations above are then repeated for the individual subframes, and desired gray scale display is performed with the combinations of all the subframes in a frame period.
Namely, in the liquid crystal display device according to the subframe driving method, all of the subframes in a frame period are preallocated to the same predetermined period or a different predetermined period. In the pixels, display is performed on all the subframes in the maximum gray scale display, display is not performed on all the subframes in the minimum gray scale display, and subframes for display are selected according to the gray scale for display in the case of the other gray scales. In the previously existing liquid crystal display device, inputted data is digital data expressing a gray scale, and the method is also a digital driving method in a two-stage latch configuration.
However, in the previously existing liquid crystal display device, since the two latches in the pixels are configured of static random access memories (SRAM), the number of transistors is increased and it is difficult to downsize the pixels.
Moreover, in the pixel above, generally, a silicon backplane including shift registers, for example, is prepared in large-scale semiconductor integrated circuit (LSI) processes. However, in probe inspection after a wafer is prepared, there is a problem that pixel inspection is not performed normally. This is because there is a possibility that the SRAM is rewritten due to electric charges accumulated on a column data line. Because when the pixel inspection is performed, data written to the SRAM is read out from the column data line after the data is input to the column data line and the input data is written to the SRAM.
In the description of Japanese Patent Application National Publication (Laid-Open) No. 2001-523847, a two-switch SRAM including two complementary bit lines is described. In contrast to this, here, the case of a one-switch SRAM configured of a single bit line and a single switch is considered.
For example, in the case of a full high definition (FHD) liquid crystal display device, the number of pixels lengthwise on the screen is 1,080 pixels, and the capacitance of the individual column data lines is about 1 pF. For example, an SRAM is configured of a switching transistor connected to a column data line at zero volt at low level and two inverters in which an input terminal of one inverter is connected to an output terminal of the other inverter. In these two inverters, suppose that the voltage of the input terminal of the one inverter connected to the switching transistor is at high level at a voltage of 3.3 V. In this case, when the switching transistor is turned on, the column data lines are charged at about 1 pF of electric charge capacitance described above from a P-channel MOS field effect transistor (in the following, referred to as a P-MOS transistor) configuring the other inverter whose output terminal is connected to the switching transistor.
At this time, since the driving force of the transistor configuring the other inverter is smaller than the driving force of the transistor configuring the one inverter, charging time is prolonged to cause incomplete charging, the voltage of the input terminal of the one inverter is below the turnover voltage, and the voltage (namely, data that has to be written to the SRAM) of the input terminal of the one inverter is rewritten. Thus, data on the SRAM is not enabled to be output to the column data line, and pixels are not accurately inspected.
The present invention is made on the viewpoints above, and it is an object to provide a liquid crystal display device and a pixel inspection method therefor that can downsize a pixel as compared with a pixel using two SRAMs in the pixel and can accurately inspect pixels.